Clock data recovery (CDR) is an important block in a receiver system for high-speed serial communications. The CDR block generates the correct sampling clock phase for data recovery. The quality of the high-speed serial communication link can be sensitive to the sampling dock phase, especially in the presence of jitter and noise.
One type of existing CDR is an edge-sampled CDR. An edge-sampled CDR oversamples the analog input waveform to generate the correct data sampling dock and recover the transmitted data. The edge-sampled CDR assumes the data to be sampled as around the center between zero-crossing points. The resulting oversampled system consumes more clocking power than a system operating at the symbol rate (also referred to as baud-rate). Further, as the channel loss profile changes, the analog waveform to be sampled is not necessarily symmetric. Thus, maintaing the data sampling dock at the center between zero-crossing points can be sub-optimal.